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HN58C65 Series
8192-word x 8-bit Electrically Erasable and Programmable CMOS ROM
ADE-203-374A (Z) Rev. 1.0 Apr. 12, 1995
Description
The Hitachi HN58C65 is a electrically erasable and programmable ROM organized as 8192-word x 8-bit. It realizes high speed, low power consumption, and a high level of reliability, employing advanced MNOS memory technology and CMOS process and circuitry technology. It also has a 32-byte page programming function to make its erase and write operations faster.
Features
* * * * * * * * * * * * Single 5 V Supply On chip latches: address, data, CE, OE, WE Automatic byte write: 10 ms max Automatic page write (32 byte): 10 ms max Fast access time: 250 ns max Low power dissipation: 20 mW/MHz typ (Active) 2.0 mW typ (Standby) Data polling and Ready/Busy Data protection circuity on power on/power off Conforms to JEDEC byte-wide standard Reliable CMOS with MNOS cell technology 105 erase/write cycles (in page mode) 10 year data retention
Ordering Information
Type No. HN58C65P-25 HN58C65FP-25 Note: Access Time 250 ns 250 ns Package 600 mil 28 pin plastic DIP (DP-28) 28 pin plastic SOP*1 (FP-28D/DA)
1. T is added to the end of the type no. for a SOP of 3.0 mm (max) thickness.
HN58C65 Series
Pin Arrangement
HN58C65P/FP Series RDY/Busy A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 (Top View) VCC WE NC A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3
Pin Description
Pin Name A0 - A12 I/O1 - I/O7 OE CE WE VCC VSS NC RDY/Busy Function Address input Data input/output Output enable Chip enable Write enable Power (+5 V) Ground No connection Ready/Busy
2
HN58C65 Series
Block Diagram
I/O0 VCC VSS OE CE WE Control Logic and Timing I/O7 RDY/Busy
High Voltage Generator I/O Buffer and Input Latch
A0 A4 Address Buffer and Latch A5 A12
Y Decoder
Y Gating
X Decoder
Memory Array
Data Latch
Mode Selection
Pin Mode Read Standby Write Deselect Write inhibit Data polling Note: CE VIL VIH VIL VIL X X VIL OE VIL X
*1
WE VIH X VIL VIH VIH X VIH
RDY/Busy High-Z High-Z High-Z to V OL High-Z
I/O Dout High-Z Din High-Z
VIH VIH X VIL VIL
High-Z VOL
-- Data out (I/O7)
1. X = Don't care
3
HN58C65 Series
Absolute Maximum Ratings
Parameter Supply voltage Input voltage
*1 *3 *1
Symbol VCC Vin Topr Tstg
Value -0.6 to +7.0 -0.5 to +7.0 0 to +70 -55 to +125
*2
Unit V V C C
Operating temperature range Storage temperature range
Notes: 1. With respect to V SS 2. -3.0 V for pulse width 50 ns. 3. Including electrical characteristics and data retention.
Recommended DC Operating Conditions
Parameter Supply voltage Input voltage Symbol VCC VIL VIH Operating temperature Topr Min 4.5 -0.3 2.2 0 Typ 5.0 -- -- -- Max 5.5 0.8 VCC + 1 70 Unit V V V C
4
HN58C65 Series
DC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%)
Parameter Input leakage current Output leakage current VCC current (Standby) VCC current (Active) Symbol I LI I LO I CC1 I CC2 Min -- -- -- -- Typ -- -- -- -- Max 2 2 1 8 Unit A A mA mA Test Conditions VCC = 5.5 V Vin = 5.5 V VCC = 5.5 V Vout = 5.5/0.4 V CE = VIH, CE = VCC Iout = 0 mA Duty = 100% Cycle = 1 s at VCC = 5.5 V Iout = 0 mA Duty = 100% Cycle = 250 ns at VCC = 5.5 V
--
--
25
mA
Input low voltage Input high voltage Output low voltage Output high voltage Note:
VIL VIH VOL VOH
-0.3 *1 2.2 -- 2.4
-- -- -- --
0.8 VCC + 1 0.4 --
V V V V I OL = 2.1 mA I OH = -400 A
1. -1.0 V for pulse width 50 ns
Capacitance (Ta = 25C, f = 1 MHz)
Parameter Input capacitance
*1 *1
Symbol Cin Cout
Min -- --
Typ -- --
Max 6 12
Unit pF pF
Test Conditions Vin = 0 V Vout = 0 V
Output capacitance Note:
1. This parameter is periodically sampled and not 100% tested.
AC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%)
Test Conditions * * * * Input pulse levels: 0.4 V to 2.4 V Input rise and fall time: 20 ns Output load: 1TTL gate + 100 pF Reference levels for measuring timing: 0.8 V and 2 V
5
HN58C65 Series
Read Cycle
Parameter Address to output delay CE to output delay OE to output delay Address to output hold OE, CE high to output float Note:
*1
Symbol t ACC t CE t OE t OH t DF
Min -- -- 10 0 0
Max 250 250 100 -- 90
Unit ns ns ns ns ns
Test Conditions CE = OE = VIL, WE = VIH OE = VIL, WE = VIH CE = VIL, WE = VIH CE = OE = VIL, WE = VIH CE = VIL, WE = VIH
1. t DF is defined at which the outputs archieve the open circuit conditions and are no longer driven.
Read Timing Waveform
Address t ACC CE tCE OE tOE WE High tDF tOH
Data Out
Data Out Valid
6
HN58C65 Series
Write Cycle
Parameter Address setup time Address hold time CE to write setup time (WE controlled) CE hold time (WE controlled) WE to write setup time (CE controlled) WE hold time (CE controlled) OE to write setup time OE hold time Data setup time Data hold time WE pulse width (WE controlled) CE pulse width (CE controlled) Data latch time Byte lode cycle Byte lode window Write cycle time Time to devce busy Write start time Symbol t AS t AH t CS t CH t WS t WH t OES t OEH t DS t DH t WP t CW t DL t BLC t BL t WC t DB t DW Min*1 0 150 0 0 0 0 0 0 100 20 200 200 100 0.30 100 -- 120 150 Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max -- -- -- -- -- -- -- -- -- -- -- -- -- 30 -- 10 -- --
*2
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns s s ms ns ns
Test Conditions
Notes: 1. Use this device in longer cycle than this value. 2. t WC must be longer than this value unless polling technique is used. This device automatically completes the internal write operation within this value.
7
HN58C65 Series
Byte Write Timing Waveform (1) (WE Controlled)
t WC Address t CS CE t AS tWP WE t OES OE t DS Din t DW RDY/Busy High-Z t DB High-Z t DH t OEH t BL t AH t CH
8
HN58C65 Series
Byte Write Timing Waveform (2) (CE Controlled)
Address t WS CE t AS WE t OES OE t DS Din t DW High-Z t DB High-Z t DH t OEH t AH t CW t WH t BL t WC
RDY/Busy
9
HN58C65 Series
Page Write Timing Waveform (1) (WE Controlled)
Address A5 to A12
Address A0 to A4 t AS WE t CS CE
t AH t WP t DL t CH
t BLC
t BL
t WC
t OEH t OES OE
t DS
Din t DH RDY/Busy High-Z t DB t DW High-Z
10
HN58C65 Series
Page Write Timing Waveform (2) (CE Controlled)
Address A5 to A12
Address A0 to A4 t AS CE t WS WE
t AH t CW t DL t WH
t BLC
t BL
t WC
t OEH t OES OE
t DS
Din t DH RDY/Busy High-Z t DB t DW High-Z
11
HN58C65 Series
Data Polling Timing Waveform
Address
An
An
An
CE
WE t BL OE t OE I/O7 Din X Dout X t WC Dout X t DW t OES
Functional Description
Automatic Page Write Page-mode write feature allows 1 to 32 bytes of data to be written into the EEPROM in a single write cycle. Following the initial byte cycle, an additional 1 to 31 bytes can be written in the same manner. Each additional byte load cycle must be started within 30 s of the preceding rising edge of the WE. When CE or WE is high for 100 s after data input, the EEPROM enters write mode automatically and the input data are written into the EEPROM. Data Polling Data polling allows the status of the EEPROM to be determined. If EEPROM is set to read mode during a write cycle, an inversion of the last byte of data to be loaded outputs from I/O7 to indicate that the EEPROM is performing a write operation. RDY/Busy Signal RDY/Busy signal also allows the status of the EEPROM to be determined. The RDY/Busy signal has high impedance, except in write cycle and is lowered to VOL after the first write signal. At the end of a write cycle, the RDY/Busy signal changes state to high impedance.
12
HN58C65 Series
WE, CE Pin Operation During a write cycle, addresses are latched by the falling edge of WE or CE and data is latched by the rising edge of WE or CE. Write/Erase Endurance and Data Retention Time The endurance is 105 cycles in case of the page programming and 3 x 103 cycles in case of byte programming (1% cumulative failure rate). The data retention time is more than 10 years when a device is pageprogrammed less than 104 cycles. Data Protection 1. Data Protection against Noise on Control Pins (CE, OE, WE) during Operation During readout or standby, noise on the control pins may act as a trigger and turn the EEPROM to progam mode by mistake. To prevent this phenomenon, this device has a noise cancelation function that cuts noise if its width is 20 ns or less in program mode. Be careful not to allow noise of a width of more than 20 ns on the control pins.
WE CE
5V 0V
5V OE 0V
20 ns max
13
HN58C65 Series
2. Data Protection at VCC On/Off When V CC is turned on or off, noise on the control pins generated by external circuits (CPU, etc.) may act as a trigger and turn the EEPROM to program mode by mistake. To prevent this unintentional programming, the EEPROM must be kept in an unprogrammable state while the CPU is in an unstable state.
VCC
CPU RESET
* Unprogrammable
* Unprogrammable
*The EEPROM should be kept in unprogrammable state during VCC on/off by using CPU RESET signal.
In addition, when V CC is turned on or off, the input level of on control pins must be held as shown in the table below.
CE OE WE X: Don't care. VCC: Pull-up to VCC level VSS : Pull-down to V SS level. VCC X X X VSS X X X VCC
14
HN58C65 Series
Package Dimensions
HN58C65P series (DP-28)
35.60 36.50 Max
Unit: mm
28
15 13.40 14.60 Max
1 1.90 Max
1.20
14 2.54 Min 5.70 Max 15.24
0.51 Min
0.25 - 0.05 0 - 15
+ 0.11
2.54 0.25
0.48 0.10
HN58C65FP Series (FP-28D)
18.30 18.75 Max 28 15 8.40
Unit: mm
2.50 Max
1 1.12 Max
14
0.17 - 0.07
+ 0.08
11.80 0.30 1.70 0 - 10
1.27
0.40 - 0.05
+ 0.10
0.20 0.10
1.00 0.20
0.20 M 0.15
15
HN58C65 Series
HN58C65FP Series (FP-28DA)
18.00 18.75 Max 28 15 8.40
Unit: mm
1 1.27 Max
14
3.00 Max
+ 0.08 - 0.07
11.80 0.30 1.70 0 - 10
1.27 0.10
0.40 - 0.05
0.20 0.10
+ 0.10
0.17
1.00 0.20
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